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PROCESSORS

Pentium II
Slot 1

Internal RISC architecture
CISC-RISC translator
Based on Pentium Pro processor.
Intro of MMX instruction support
Slot interconnect interface
Integrated L2 512 KB cache mounted directly on slot circuit board
Full clock multiplier locking after first intro of chip.
.28-micron circuit pathways
Core voltage .28v

LX chipset designed for 66 Mhz front-side bus

100 Mhz Pentium II

BX chipset and VIA's Apollo Pro 133  for release of 133-Mhz front side bus.
.25-micron circuit design

Pentium II Klamath - 233 Mhz to 300 Mhz
No multiplier lock
FSB - 66 Mhz
242-pin Slot 1
Some 300 Mhz were locked

Pentium II Deschutes 300 - 333 Mhz
66 -  Mhz FSB
2.0 volts
multiplier locking
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Pentium II Deschutes 450 Mhz
100 Mhz front side bus

Celeron Covington 266 mHZ
242 pin slot 1
370 pin PPGA
2.0 volts
66 MHZ FSB
No level 2 cache
Locked multipliers

Covington 300 Mhz
100 Mhz FSB

Celeron Mendocino 300 - 533 Mhz
66 Mhz FSB
242 Pin slot 1
370 pin PPGA
MMX
Locked multiplier
L2 cache - 128-KB in the processor core
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Pentium III
Katmai
SSE multimedia instructions
100 Mhz FSB
Pentium III 450 - 600 Mhz was 100 MHZ FSB
Pentium III 533b and 600b Mhz was 133 Mhz
242 PIN SLOT 1
VIA Apollo Pro 133A
Intel I815 and i820 chipsets
I820 RAMBUS memory support

Pentium III Coppermine
Level 2 cache internal to core die
Slot 1
370-pin FCPGA
133 Mhz FSB

500e- 850e
100 Mhz FSB
locked multiplier

533eb
600eb
667eb - ACTUALLY A 666eb
1130eb  - limited quantities produced
133 Mhz FSB

Celeron II

533 - 1300+
66 Mhz FSB
370 pin FCPGA
Locked multiplier
.18 micron

800e - 1100E
100 mhz FSB

Pentium III Celeron / Tulatin
Hardware data prefetch
370 PIN FCPGA2
1130 - 1260 Mhz

Pentium 4 Willamette
1300-2000 mHZ
Double-speed integer execution
SSE2 streaming multimedia instructions
Trace cache architecture
Extremely long pipeline
Multiplier locked
100 Mhz Quad Data Rate bus
400 Mhz FSB speed
423 pin PGA
478 pin PGA
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Pentium 4 Northwood

1600-3000 Mhz
400 Mhz FSB speed
478 pin PGA

Northwood "B"

533 QDR
2.26-2.8 ghz


Xeon
Slot 2 in earlier chips
370 pin FCPGA later
Massive level 2 cache
Symmetric multithreading in 2+Ghz models
I860 chipset
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AMD

K5 SERIES

One of the most efficient integer execution units ever made.
Lack of a full-pipelined floating point unit.

K6 SERIES

MMX enhancements.
Split voltage interface to maintain motherboard compatibility
With Intel's Premium MMX
Rather dismal floating point unit

K6+

Added 3DNow! DSP standards
K6-2+ - included an on-die 128 KB Level 2 cache memory architecture.

K6-2

Streaming multimedia instruction set.
3Dnow! Instruction set extended the floating point capabilities
100 MHz FSB
Compatible with existing Socket 7 motherboards
Primary limitation is memory bandwidth performance.
One-tier internal cache memory buffer, with the second-level buffer surface-mounted on the
Motherboard. The Level 2 cache is accessed at the FSB bus rate because the chipset handles the transaction.
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K6-3

Level 2 cache embedded inside the processor core. This  internal L2 cache operates at the same rate as the core, increasing the cache memory latency and bandwidth exponentially compared to the K6-2. The cache memory mounted on the motherboard became a third-tier cache acting as an intermediary between the fast processor and slow system memory.

K7 ATHLON

Parallel execution
Based on DEC AlphaEV6 motherboard architecture
32-bit
EV6 separated each relevant system bus. Buses are still interlinked through a base timing configuration for deriving transfer rates. The processor bus operates in a DDR mode that transfers information on both the rising and falling edges of the clock signal.
Latest Athlon architectural revisions have expanded the DDR signaling technique to the memory bus.

Uses Slot A motherboard interface
The multiplier was physically locked. Determined by the configuration of certain resistors found on the backside of the processor circuit board.
The Athlon derives its L2 cache operational frequency through a fractional process, as the comparatively slow cache memory is mounted on the processor's printed circuit board. The cache memory is incapable of sustaining operation at the processor's core rate, this AMD was forced into a frequency-scaling paradigm .

500 - 700 MHz
100 MHz FSB
242- pin Slot A Cartridge

K75 ATHLON

500 - 1000 MHz
100 MHz FSB
242-pin Slot A Cartridge
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ATHLON THUNDERBIRD

Level 2 cache memory integrated into the processor core.
256 K cache but the internal cache operates at the core frequency rate. The increase in bandwidth and decrease in latency improved performance dramatically.

650 - 1400 MHz
100 MHz FSB
462-Pin Socket A
242-pin Slot A cartridge

The 1300 and 1400 MHz chips were only available in 462-pin Socket A.

ATHLON THUNDERBIRD "B"

1000 - 1400 MHz
133 MHz FSB
462-Pin Socket A

ATHLON DURON SPITFIRE

A Thunderbird chip with on-die Level 2 cache of 64 KB.

550-950 MHz
100 MHz FSB
462-pin Socket A

ATHLON PALOMINO/MP/XP

Hardware data pre-fetch mechanism in the execution pipeline. This pre-fetch circuitry allows the Palomino to speculate and buffer certain data packets.
Streaming multimedia instruction set
3Dnow!Professional expands the base set to include binary compatibility with the Intel SSE specification.
Multiplier locking.
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PALOMINO MP

Multiprocessing. This processor will operate in symmetric multiprocessor configurations.  

1000 - 1733 MHz
133 MHz FSB
462-Pin Socket A

DURON MORGAN

Thunderbird core with a 64 KB cache.
3Dnow!Professional
Hardware data pre-fetch

1000 - 1300 MHz
100 MHz FSB
462-Pin Socket A

ATHLON THOROUGHBRED

Multiplier locked
Rev A and Rev B.
Rev B added an additional metal layer within the processor to optimize electrical properties.
Before Nov 02 Thoroughbred was 133 MHz FSB. After that it was 166 MHz.

THOROUGHBRED REV A

1700 - 2200
133 MHz FSB
462 Pin Socket A

REV B

2000 - 2600 MHz
133 MHz FSB
462 Pin Socket A

VIA C3

733 - 933 MHz
100 MHz FSB
370 Pin Socket


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Last modified: July 07, 2011