Memory is a high-speed electronic storage for instructions and data that is accessed and acted

on by the processor subsystem and certain I/O devices. Memory is generally governed by the

CPU/chipset combination and, due to its influence on system performance is designed to meet

two key criteria. The first criterion is memory access speed determined by the data width, access

time, and cycle time; the second criterion is reliability.

Applications are loaded into system memory, and many software environments utilize different

forms of caching in memory to improve overall performance. The processing subsystem utilizes

the system memory as an external cache and is dependent on the access speed of the memory

when accessing this cache and the available on-die processor cache that may minimize external

calls. The memory bus speed determines the base speed of memory access. Further improvements

in access speed may be realized by writing data in parallel to different memory addresses improving

overall system performance. Correctly calculating the amount of memory required for a specific

server application is vital as many operating systems utilize the hard drive subsystem to compensate

Memory is a high-speed electronic storage for instructions and data that is accessed and acted

on by the processor subsystem and certain I/O devices. Memory is generally governed by the

CPU/chipset combination and, due to its influence on system performance is designed to meet

two key criteria. The first criterion is memory access speed determined by the data width, access

time, and cycle time; the second criterion is reliability.

Applications are loaded into system memory, and many software environments utilize different

forms of caching in memory to improve overall performance. The processing subsystem utilizes

the system memory as an external cache and is dependent on the access speed of the memory

when accessing this cache and the available on-die processor cache that may minimize external

calls. The memory bus speed determines the base speed of memory access. Further improvements

in access speed may be realized by writing data in parallel to different memory addresses improving

overall system performance. Correctly calculating the amount of memory required for a specific

server application is vital as many operating systems utilize the hard drive subsystem to compensate

for requirements in excess of available memory. The 

performance penalties incurred by insufficient

memory are extreme considering the vast difference between disk and memory data access speeds.

The core of the server system is extremely sensitive to data corruption, and data errors in the

memory subsystem can cause a server operating system or application to hang. Memory with error

correcting code (ECC) is utilized in server systems to correct single-bit memory errors and detect

multiple bit errors found in a memory chip. By reporting errors to the management subsystem,

faulty memory generating single-bit errors can be corrected, preventing critical server failure. It is

therefore highly recommended that servers use ECC memory. Non-ECC memory is considered

acceptable for network appliances and desktop computers.

The I/O subsystem supports the connection between key server components and the processing

environment. The overall performance of a server is largely influenced by the rate of data transfer

between system components. The data bus forms the communication pathway between server

components. There are many different data buses in a real server and they have a significant effect

on overall performance and room-to-grow benefits. The processor front-side bus and the rate of

data exchange between the processing and memory subsystems are critical to system performance.

I/O devices communicate within a server system through separate data buses connected to a

data switching hub known as the I/O control hub. Unlike desktops, a real server commonly performs

multiple tasks within a network environment requiring more than one I/O data bus to support the

I/O generated as part of its normal function. The factors influencing server performance within the I/O

subsystem are the available data bus bandwidth, the number of independent data buses available

for I/O devices, and the I/O Control Hub data throughput capacity.

The key to realizing data bus performance is to make sure that the I/O requirements are correctly

calculated and I/O generating components are effectively distributed across available I/O bus

segments. An example of correct I/O calculation and distribution is the inclusion of a high-speed

disk subsystem intended to enhance server performance, the gains may of which not be realized if

the I/O subsystem does not allow high-speed data access across the I/O buses. Since a server is

normally available within a network environment, the speed of network access can be hindered if

the I/O buses cannot support high-bandwidth data transfers.

Within a real server, each PCI segment has a bandwidth limitation depending on its implementation.

The chart below details PCI segment bandwidth.

A server hosting a high volume transactional database may experience many network requests

resulting in high data volumes on the internal system I/O and the potential for a substantial amount

of data transfers to disk. Both data I/O loads should be handled concurrently, implying that multiple

I/O buses are required in real server design. Most desktop systems have a single PCI 32-bit, 33-MHz

segment providing a maximum peak bandwidth of 133MB/s. It is therefore possible to saturate the

I/O capability of a desktop by merely adding a single Gigabit network adaptor and a single-channel

Ultra320 RAID card on this PCI bus. In contrast an Intel Server Board SE7501HG2 has three

separate data buses that incorporate a 32-bit, 33-MHz bus; a 64-bit, 100-MHz bus and a 64-bit,

133-MHz bus all connected to an I/O control hub that facilitates concurrent communications. This

illustrates a fundamental difference in desktop and real server design—the I/O capability of a real

server is clearly designed to handle the data transfer rates required by its intended environment.

Intel server boards have multiple PCI segments connected to high-bandwidth I/O control hubs to

facilitate the distribution of workloads and bandwidth demands and enhancing overall real server

performance. The Intel E7501 Chipset provides the features listed in the table below.

PCI Express* is an emerging interconnect technology designed to provide universal connectivity for

use as a chip-to-chip and adapter card interconnect. PCI Express architecture provides the bandwidth

requirements beyond those achievable with traditional parallel PCI. It is expected to provide

high-performance connectivity to data center technologies such as Ethernet*, InfiniBand* architecture

and Fibre Channel* on Intel architecture-based platforms starting in 2004. PCI Express architecture

is a high-performance, highly flexible, scalable, reliable, stable and cost-effective general purpose

I/O architecture that is considered the natural evolution of PCI.