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At 90 nanometers and below, leakage power management is essential in the ASIC design process. As voltages scale downward with the geometries, threshold voltages must also decrease to gain the performance advantages of the new technology. This reduction in threshold voltages has led to an exponential increase in leakage current in the transistors. Thinner gate oxides have led to an increase in gate leakage current, as well.
While ASIC power concerns were once primarily confined to the domain of battery-supplied applications — often mobile, handheld devices — that tend to demand more power-efficient circuits to maximize battery lifetime, the relationship between speed and leakage power has caused many high-speed ASIC designers to reconsider their design flows and methodologies.
In this article, we provide an overview of the leakage power challenges in designs at 90nm and below, and discuss the essentials of a leakage power management solution: the technologies, techniques, and tools needed to address leakage power in today's advanced designs.
Since the shift to CMOS in the 1980's, designers have enjoyed the benefits of a technology whose power consumption was largely defined by the level of switching activity in the circuit. In many cases, standby power was not an issue. When switching activity stopped, standby power was negligible, with the reverse-biased junctions between the drain and base of the transistors accounting for a large portion of any leakage current.
As technologies have scaled down to thinner line widths, voltages have also scaled down to reduce the strength of the electric fields created in the new circuits, as well as to reduce dynamic power. Figure 1 shows a simple view of a CMOS transistor. As gate oxide thicknesses (tox) decrease to as low as 12 angstroms in some 90nm processes, the voltages across the gate must be reduced to keep the electric fields from becoming too high for the insulating material.
For many mainstream designs, the scaling of supply voltages started with technologies under 0.5 microns, for which 5 volts (V) were reduced to 1V and lower. To gain the expected performance advantages for each new process generation, it has been necessary to reduce the transistor threshold voltages as well. Transistors designed to operate with threshold voltages of 1.25V — as in a 5V technology — are not useable in a 1V technology.
Figure 1 — Simple view of a
CMOS transistor.
Scaling of threshold voltages has been a large factor in the increasing leakage currents seen in recent CMOS technology generations. Figure 2 shows the relationship between performance and leakage power for typical 90 nm processes. Typically, sub-threshold leakage increases exponentially with every 65 milli-Volt (mV) decrease in threshold voltage. As the graph shows, going from an approximate gate delay of 25 picoseconds down to 8 picoseconds incurs over four orders of magnitude increase in leakage.
Working with technologies that have large standby currents is not a new concept. Designers who have used a bipolar junction technology like emitter-coupled logic (ECL) or another field effect transistor (FET) technology like nMOS are very familiar with the concept of currents constantly flowing in their circuits.
For designers who have spent their careers mostly designing in CMOS, the concept of large standby currents can be a rather new and startlingly disappointing realization, especially when chips arrive from the foundry with much higher power dissipation. A comprehensive leakage power management flow becomes essential to eliminate such surprises.
Essentials of leakage power
management
Current process technologies are pushing designers into considering new design methods to reduce leakage power. As Figure 2 indicates, trading off speed is an effective way to reduce leakage power. To make use of this concept, it is necessary to create a library with a richer selection of cells based on speed and leakage characteristics.
To this end, foundries are now offering processes that make more than one threshold type of transistor available in nMOS and pMOS. These different transistor types are then used to create separate cells with the same functionality but with different speed and leakage characteristics.
Figure 3 shows a plot of library cells for a 90nm process based on the average leakage of the low Vth cells. The higher leakage cells are implemented using low Vth transistors and are plotted in yellow. The blue plot indicates the leakage characteristics for the corresponding high Vth based cells.
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